In the fabrication of ultra-large scale-integration (ULSI) circuits, vertical stacking, or integration, of metal wiring circuits to form multilevel interconnection has recently become a common approach to increase circuit performance and increase the functional complexity of the circuits. One drawback of multilevel interconnection is the loss of topological planarity resulting from various photolithographic and etching processes. To alleviate these problems, the wafer is planarized at various stages in the fabrication process to minimize non-planar topography and thus its adverse effects. One of the first steps in the planarization process is to coat a liquefied dielectric material, such as silicon dioxide, on the surface of the wafer, using the so-called spin-on-glass (SOG) process, by which a coating machine is used to spin the wafer while the liquefied silicon dioxide is being applied onto the wafer. After the SOG process, the wafer is placed on top of a hot plate, so as to evaporate the solvent contained in the SOG layer so as to solidify the SOG layer. Other non-glass material, typically a polymer material, can be used in forming such SOG layer.
FIGS. 1A and 1B show the top view and side view, respectively, of a conventional hot plate used in conjunction with an SOG coater. After the wafer 1 is SOG coated, it is placed on top of a loader robot 2 which moves along the tracks 3 formed in the hot plate 4. After the loader robot 2 moves the SOG-coated wafer 1 to the predetermined place, it then drops the wafer 1 onto the surface of the hot plate 4, where the solvent contained in the liquefied SOG layer is evaporated to form a solidified SOG layer.
Because of the ever-increasing consumer demand and expectation for better and cheaper IC products, a semiconductor manufacturer must look at every possible avenue to increase production yield rate so as to reduce the overall product cost. After having carefully examined a large number of production failures, the inventor of the present invention discovered that one of the common types of failures was related to micro-cracks that occurred in the solidified SOG layer and which can be visualized from a scanning electronic microscope. Because an SOG layer is typically required in each vertical integration, the possibility of failure due to a damaged SOG layer multiplies in today's high density IC chips. At the present time, this problem has not be identified, nor has any solution been proposed, by the semiconductor industry.